D/A Converter. .

These devices are "conductors" between analog and digital worlds of electricity.

The bottom line is that sensors, motors, lights and many other devices use analog signal, that is, for example, a voltage with a level from 0V to 12V, while digital FPGAs, microcontrollers and microcircuits need constant voltage levels, for example 0V and 5V, which are logical 0 and 1 respectively.

Example 1 DAC

Imagine that we are faced with the task of controlling the brightness of an LED:

• 10 levels (gradations) LED brightness
• maximum voltage via LED 9V
• controlled by a microcontroller and two buttons "+1 brightness level", "-1 brightness level"

So, the LED operates on a voltage of 0 to 9V. It is easy to guess that 10 gradations of brightness are 10 voltage levels that we apply to the LED - 0V, 1V, ..., 9V

The microcontroller outputs either 0V or 5V. But not 1V, 3V, 4V or 9V. But the microcontroller has a lot logical conclusions that we can connect to DAC at and convert logic in analog signal.

At digital-to-analogue converter there are, for example, 4 input pins for connecting logic signals and 2 pins for output analog voltages from 0 to 15V - conclusions "+" and "-".

Here is your job DAC a: when we serve all 4 legs logical 1, then the voltage level analog output signal is maximum( 15V in our case), when we serve 0 - the minimum, i.e. 0V

Now the most interesting. Each input terminal DAC but there is a "weight" for the output signal. For example, the top output "weighs" 8V (that is, if you apply a logical 1 only to the 1st output, then we will get 8V at the output), next below 4V, next 2V, and last low 1V. Now add up these numbers and get 15V.

We need to get levels 0V, 1V, 2V, 3V, 4V, 5V, 6V, 7V, 8V and 9V.

This means that the inputs DAC must be coded according to the following table

The buttons "+1 brightness level", "-1 brightness level" will add or subtract 1 unit from the output digital microcontroller signal. This signal will be applied to the inputs DAC. Exit DAC will be connected to the LED. Mission accomplished!

Example 2. ADC

Analog to digital converterworks in reverse. We apply a changing voltage level to the input, we get logic at the output (bits) +5V and 0V, or logic 1 and 0

Let's set the task to take readings from the temperature sensor:

• the sensor shows the temperature from 0C to 30C
• at 0C the sensor outputs 0V, at 30C it outputs 15V
• the signal must be received by the microcontroller in digital form (logical 1 and 0, voltage + 5V and 0V)

ADC has two input pins for receiving an analog signal with a voltage, for example, from 0 to 15V and, in our case, 4 pins for the output digital logic signal. That is, a four-bit parallel code signal.

We connect the output from our sensor to the analog input ADC, and a digital four-digit output from ADC connect to the microcontroller. And we are already accepting readings from the sensor in digital form on the mikrik. The data in the process will correspond to the table below.

An analog-to-digital converter is a device designed to convert a physical quantity that changes continuously over time into equivalent digital code values. An analog value can be voltage, current, angular displacement, gas pressure, etc.

The process of analog-to-digital conversion involves the sequential execution of the following operations (Fig. 13.5):

Sampling the values ​​of the original analog value at some given time points, i.e. signal sampling in time,

Quantization (rounding of the converted value to some known values) of the value of the analog value obtained at discrete times by level,

Encoding - replacement of the found quantum values ​​with some numerical codes.

Rice. 13.5. The principle of analog-to-digital conversion.

The error of the integrating ADC is determined mainly by the change in the slope of the sawtooth voltage, which is determined by the time constant of the RC integrator (sawtooth voltage generator). Under the influence of external destabilizing factors, especially temperature, the time constant, and hence the slope of the sawtooth voltage, changes, which leads to significant conversion errors. Therefore, at present, the principle of double integration is used to build integrating ADCs.

Principle of operation double integration ADC consists in the fact that first, during a certain fixed time interval T 1, the analog converted value U x is integrated, and then the reference (reference) voltage of opposite polarity U op is integrated. The time interval T 2 is proportional to the converted value U x .

Figure 13.11. Structural diagram of the ADC of double integration (a) and the timing diagram of its operation (b) Indeed, during the time interval T 1, the voltage at the output of the integrator changes according to a linear law:

During the time interval T 2, the output voltage at the output of the integrator changes from Uout.int.max to 0, i.e.

Consequently,

Thus, the time interval T 2 depends on the constant T 1 /U op and the variable U x and does not depend on the parameters of the integrator. This can be seen in the graph shown in Fig. 13.12.

Figure 13.12. The voltage at the output of the integrator at a time constant τ 1 = R 1 * C 1 (1) and at τ 2 = R 2 * C 2 (1) The double-integration ADC provides high conversion accuracy under industrial noise conditions in a wide temperature range and is widely used in measuring technology and automated control systems.

For example, the basis of all multimeters is the double-integration ADC, made on the K572PV2 or K572PV5 chip. The ICs are almost the same, but the first one drives LEDs and the second drives LCDs.

The K572PV2 microcircuit, together with a reference voltage source, several resistors and capacitors, performs the functions of a double-integration ADC with automatic zeroing of the op-amp and determination of the input signal polarity.

Main technical parameters of IS:

Bit depth - 3.5 decimal places,

Input impedance - 50Mohm,

Input voltage - ±1.999Uop(V),

Performance - (2-9) Hz,

Current consumption - 1.8 mA

Supply voltage - 9V.

Figure 13.13. IS K572PV2 (a) and output voltage at the generator output (b)

The operation of the IC occurs under the influence of clock pulses f of the internal pulse generator in three stages:

At the first stage T 1 , lasting 4000 periods f ty, the voltage U x is integrated,

At the second stage, lasting from 0 to 8000 periods, f ti is the integration of the reference voltage U op and

At the third stage, lasting from 4000 to 12000 periods f ty, the op-amp is automatically set to zero.

The entire conversion cycle takes 16,000 cycles.

Multichannel ADCs are widely used to convert several analog values ​​of the same type. Such ADCs include an analog switch and one of the ADCs discussed above.

Figure 13.14. Multichannel ADC

The conversion occurs sequentially parameter by parameter. The analog switch alternately connects all input signals to the ADC input through an amplifier.

For convenience, the article will be divided into 2 parts.

Part I

ADC or analog-to-digital conversion.

In analog equipment, analog sound has the form of a continuous electrical signal, computer technology, in turn, works only with digital data - hence the sound in the computer is digital.

I think you already have some confusion between "sounds". In order to avoid misunderstanding, let's consider what is digital sound and how analog is converted "to digital".

digital audio- a method of representing an audio signal by means of discrete numerical values ​​of its amplitude.

As usual, I will try to explain everything in a simpler way. I repeat a little.

A sound wave is a complex function depicting the dependence of its amplitude on time.

To digitize this wave, it is necessary to describe it, keeping a discrete value to specific points.

The value of the amplitude of the sound wave must be measured at each time point, and the resulting value should be written as numbers. But, due to the impossibility of fixing the amplitude value with an accuracy of 100%, they have to be written in a rounded form. Which, as a result, entails small distortions of the original signal. In other words, there will be a kind of approximation of this function along the amplitude and time coordinate axes.

As you can see, the signal digitization process consists of two stages.

1.First - sampling (sampling)

2.Second - quantization.

Sampling- the process of obtaining the values ​​of the converted signal at certain time intervals. In other words, it is, as it were, a “sampling” of a signal according to given values.

Quantization- represents the process of replacing the received values ​​of the signal amplitude with the maximum approximate accuracy.

As mentioned above, when converting a signal, it is necessary to round the values ​​due to the impossibility of fixing the “real” amplitude value with ideal (in fact, infinite) accuracy. To do this, computers would need a larger amount of RAM (more than 1TB), and you can refine it indefinitely, which, as a result, entails the creation of RAM with an infinite amount of memory.

The rounding accuracy is affected by the level of quantization (or the bit depth of quantization). The greater the number of levels, the smaller the value of the amplitude is rounded, which, as a result, results in a smaller error.

Based on the foregoing, it can already be concluded that the digitization of a signal is a fixation of the amplitude of a sound wave at certain time intervals, and a record of the received one with a minimum error.

There is another conclusion to be drawn. The higher the sampling rate and quantization bit depth, the more accurate the description of the received signal.

The quality directly depends on the parameters chosen for digitization. These are the sampling rate (expressed in KHz) and the bit depth (expressed in Bits).

In other words, the higher the bit depth and sampling rate, the better the signal is obtained, and the greater the amount of digitized data. Therefore, here you should look for the "golden mean" between weight and quality.

Kotelnikov's theorem (in the English literature - the Nyquist-Shannon theorem or the sampling theorem) states that if an analog signal has a finite (limited in width) spectrum, then it can be restored uniquely and without loss from its discrete samples taken with a frequency strictly greater than twice the upper frequency.

In the “translation into normal human language”, in order to obtain the most complete information about the sound, for example, in the frequency range up to 22,000 Hz, sampling with a frequency of at least 44.1 Kg is required.

This suggests that there is no point in chasing high sampling rates much, since the frequency of 44.1 kHz covers the entire range of frequencies that a person can hear, and even a little higher.

Part II

Digital-to-analog conversion.

In order to be able to listen to the sound after digitization, it must be converted back to analog.

The analog signal can be processed by amplifiers and other analog devices and reproduced by loudspeakers.

Converts a digital signal to analog - a digital-to-analog converter (DAC). The conversion process is an inverse ADC procedure.

Modern systems play and record sound through an audio interface, whose task is to input and output audio information, i.e. This is a device for converting an analog signal to digital and vice versa.

The operation of the audio interface can be explained in simpler terms.

First, the input analog sound enters the analog input (or mixer), after which it is sent to the ADC, which quantizes and samples it .. The result is a digital audio signal that goes to the computer via the bus and digital sound is obtained.

When outputting audio information, a similar process occurs, only in the opposite direction. The data stream passes through the DAC, which converts the numbers that determine the amplitude of the signal into an electrical - analog signal.

Schematically, it all looks as shown in Fig. 1

I want to note that if the audio interface is equipped with an interface for digital data exchange, then when working with digital audio, none of its analog blocks are involved - thus, bypassing the converters, you will keep the sound almost as it is.

The article describes the device and principles of operation of analog-to-digital converters of various types, as well as their main characteristics, indicated by manufacturers in the documentation.

The analog-to-digital converter (ADC) is one of the most important electronic components in measurement and test equipment. The ADC converts the voltage (analog signal) into a code that the microprocessor and software perform certain actions on. Even if you're only working with digital signals, you're most likely using an ADC on your oscilloscope to find out their analog characteristics.

There are several basic types of ADC architecture, although there are also many variations within each type. Different types of measurement equipment use different types of ADCs. For example, a digital oscilloscope uses a high sample rate but does not require high resolution. Digital multimeters need more resolution, but you can sacrifice measurement speed. General purpose data acquisition systems typically rank between oscilloscopes and digital multimeters in terms of sample rate and resolution. This type of equipment uses a successive approximation ADC or a sigma-delta ADC. There are also parallel ADCs for applications that require high-speed analog signal processing and integrating ADCs with high resolution and noise reduction.

In Fig.1. the capabilities of the main ADC architectures are shown depending on the resolution and sampling rate.

Rice. 1. Types of ADC - resolution depending on the sampling rate

Parallel ADCs

Most high-speed oscilloscopes and some high-frequency instruments use parallel ADCs because of their high conversion speed, which can reach 5 Hz (5 x 10 9) samples/sec for standard devices and 20 Hz samples/sec for original designs. Parallel ADCs typically have a resolution of up to 8 bits, but 10-bit versions are also available.

Rice. 2. ADC parallel conversion

Rice. 2 shows a simplified block diagram of a 3-bit parallel ADC (for converters with higher resolution, the principle of operation is the same). It uses an array of comparators, each of which compares the input voltage to an individual reference voltage. Such a reference voltage for each comparator is formed on the built-in precision resistive divider. The voltage references start at half the least significant digit (LSB) and increase with each successive comparator in increments of V REF /2 3 . As a result, a 3-bit ADC requires 2 3 -1 or seven comparators. And, for example, for an 8-bit parallel ADC, 255 (or (2 8 -1)) comparators will be required.

As the input voltage increases, the comparators sequentially set their outputs to logic one instead of logic zero, starting with the comparator responsible for the least significant bit. You can imagine the converter as a mercury thermometer: as the temperature rises, the mercury column rises. On fig. 2, the input voltage falls between V3 and V4, so the bottom 4 comparators output "1" and the top three comparators output "0". The decoder converts (2 3 -1) - bit digital word from the outputs of the comparators into a binary 3-bit code.

Parallel ADCs are reasonably fast devices, but they have their drawbacks. Due to the need to use a large number of comparators, parallel ADCs consume significant power and are not practical for battery-powered applications.

When a resolution of 12, 14, or 16 bits is needed and high conversion speed is not required, and low price and low power consumption are the determining factors, successive approximation ADCs are usually used. This type of ADC is most commonly used in a variety of instrumentation and data acquisition systems. At the moment, successive approximation ADCs allow measuring voltage with an accuracy of up to 16 bits with a sampling rate from 100K (1x10 3) to 1M (1x10 6) samples/sec.

Rice. 3 shows a simplified block diagram of a successive approximation ADC. This type of ADC is based on a special successive approximation register. At the beginning of the conversion cycle, all outputs of this register are set to logic 0, except for the first (highest) bit. This generates a signal at the output of the internal digital-to-analog converter (DAC) whose value is equal to half the input range of the ADC. And the output of the comparator switches to a state that determines the difference between the signal at the DAC output and the measured input voltage.

Rice. 3. SAR ADC

For example, for an 8-bit SAR ADC (Figure 4), the register outputs are set to "10000000". If the input voltage is less than half the input range of the ADC, then the output of the comparator will be logic 0. This instructs the successive approximation register to switch its outputs to the state "01000000", which will accordingly change the output voltage from the DAC to the comparator. If the comparator output would still remain at "0", then the register outputs would switch to the state "00100000". But at this conversion cycle, the output voltage of the DAC is less than the input voltage (Fig. 4), and the comparator switches to a logic 1 state. This instructs the successive approximation register to store a "1" in the second bit and apply a "1" to the third bit. The described operation algorithm is then repeated again until the last digit. Thus, a successive approximation ADC requires one internal conversion clock per bit, or N clocks for an N-bit conversion.

Rice. 4. Conversion to ADC of successive approximations

However, the operation of the successive approximation ADC has a peculiarity associated with transients in the internal DAC. Theoretically, the voltage at the output of the DAC for each of the N internal conversion cycles should be set in the same period of time. But in fact, this interval in the first bars is much larger than in the last ones. Therefore, the conversion time of a 16-bit successive approximation ADC is more than twice the conversion time of an 8-bit successive approximation ADC.

Most measurements often do not require an ADC with the conversion speed that a successive approximation ADC provides, but a high resolution is needed. Sigma-delta ADCs can provide up to 24 bits of resolution, but are inferior in conversion speed. So, in a sigma-delta ADC at 16 bits, you can get a sampling rate of up to 100K samples/sec, and at 24 bits this frequency drops to 1K samples/sec or less, depending on the device.

Typically, sigma-delta ADCs are used in a variety of data acquisition systems and in measuring equipment (measurement of pressure, temperature, weight, etc.) when a high sampling rate is not required and a resolution of more than 16 bits is required.

The principle of operation of the sigma-delta ADC is more difficult to understand. This architecture belongs to the class of integrating ADCs. But the main feature of the sigma-delta ADC is that the sampling frequency, at which the voltage level of the measured signal is actually analyzed, significantly exceeds the sampling rate at the ADC output (sampling frequency). This sampling rate is called the resampling rate. For example, a sigma-delta ADC with a conversion rate of 100K samples/sec, which uses a resampling rate of 128 times faster, will sample the input analog signal at a rate of 12.8M samples/sec.

The block diagram of the first-order sigma-delta ADC is shown in fig. 5. An analog signal is applied to an integrator whose outputs are connected to a comparator, which in turn is connected to a 1-bit DAC in a feedback loop. Through a series of successive iterations, the integrator, comparator, DAC, and adder produce a stream of serial bits that contains information about the magnitude of the input voltage.

Rice. 5. Sigma-Delta ADC

The resulting digital sequence is then fed to a low-pass filter to suppress components above the Kotelnikov frequency (half the ADC sample rate). After removing the high-frequency components, the next node - the decimator - thins out the data. In the ADC we are considering, the decimator will leave 1 bit out of every 128 received in the output digital sequence.

Since the internal digital low-pass filter in the sigma-delta ADC is an integral part of the conversion process, the low-pass filter settling time becomes a factor to consider when hopping the input signal. For example, when switching the input multiplexer or when switching the measurement limit of the device, it is necessary to wait until several ADC samples have passed, and only then read the correct output data.

An additional and very important advantage of the sigma-delta ADC is that all its internal units can be made integrally on the area of ​​one silicon chip. This significantly reduces the cost of end devices and increases the stability of the ADC characteristics.

Integrating ADCs

And the last type of ADC that will be discussed here is the push-pull ADC. In digital multimeters, as a rule, just such ADCs are used, because. these instruments require a combination of high resolution and high noise suppression. The idea of ​​conversion in such an integrating ADC is much less complicated than in a sigma-delta ADC.

Figure 6 shows how a push-pull ADC works. The input signal charges the capacitor for a fixed period of time, which is usually one cycle of the mains frequency (50 or 60 Hz) or a multiple of it. When integrating the input signal over a period of time of this duration, high-frequency noise is suppressed. At the same time, the influence of voltage instability of the mains power supply on the conversion accuracy is eliminated. This is because the value of the integral of the sinusoidal signal is zero if the integration is carried out over a time interval that is a multiple of the period of the sinusoidal change.

Rice. 6. Integrating ADC. Green color shows interference from the mains (1 period)

At the end of the charge time, the ADC discharges the capacitor at a fixed rate, while an internal counter counts the number of clock pulses during the discharge of the capacitor. A longer discharge time therefore corresponds to a larger meter reading and a larger measured voltage (Fig. 6).

Push-pull ADCs have high accuracy and high resolution, and also have a relatively simple structure. This makes it possible to implement them in the form of integrated circuits. The main disadvantage of such ADCs is the long conversion time, due to the binding of the integration period to the duration of the power supply period. For example, for 50 Hz equipment, the sampling rate of the push-pull ADC does not exceed 25 samples/sec. Of course, such ADCs can also work with a higher sampling rate, but as the latter increases, the noise immunity decreases.

ADC specification

There are general definitions that are commonly used in relation to analog-to-digital converters. However, the specifications given in the technical documentation of ADC manufacturers can seem rather confusing. The correct choice of the ADC that is optimal in terms of its characteristics for a particular application requires an accurate interpretation of the data given in the technical documentation.

The most commonly confused parameters are resolution and accuracy, although these two characteristics of a real ADC are extremely loosely related. Resolution is not identical to precision, a 12-bit ADC may have less precision than an 8-bit ADC. For an ADC, resolution is a measure of how many segments the input range of the measured analog signal can be divided into (for example, for an 8-bit ADC, this is 28 = 256 segments). Accuracy characterizes the total deviation of the conversion result from its ideal value for a given input voltage. That is, the resolution characterizes the potential capabilities of the ADC, and the set of accuracy parameters determines the feasibility of such a potential capability.

The ADC converts the input analog signal into an output digital code. For real converters manufactured in the form of integrated circuits, the conversion process is not ideal: it is affected by both the technological spread of parameters during production and various external interference. Therefore, the digital code at the output of the ADC is determined with an error. The specification for the ADC indicates the errors that the converter itself gives. They are usually divided into static and dynamic. At the same time, it is the end application that determines which characteristics of the ADC will be considered decisive, the most important in each specific case.

Static error

In most applications, an ADC is used to measure a slowly varying, low frequency signal (eg from a temperature sensor, pressure sensor, strain gauge, etc.) where the input voltage is proportional to a constant physical quantity. Here the main role is played by the static measurement error. In the ADC specification, this type of error is defined by additive error (Offset), multiplicative error (Full-Scale), differential non-linearity (DNL), integral non-linearity (INL) and quantization error. These five characteristics allow you to fully describe the static error of the ADC.

Ideal Transfer Response of ADC

The transfer characteristic of an ADC is a function of the dependence of the code at the ADC output on the voltage at its input. Such a graph is a piecewise linear function of 2N "steps", where N is the ADC bit depth. Each horizontal segment of this function corresponds to one of the values ​​of the ADC output code (see Fig. 7). If we connect the beginnings of these horizontal segments with lines (at the boundaries of the transition from one code value to another), then the ideal transfer characteristic will be a straight line passing through the origin.

Rice. 7. Ideal transfer characteristic of 3-bit ADC

Rice. 7 illustrates the ideal transfer characteristic for a 3-bit ADC with breakpoints at code transition boundaries. The output code takes on the smallest value (000b) when the input signal is between 0 and 1/8 full scale (the maximum code value of this ADC). Also note that the ADC will reach the full scale code value (111b) at 7/8 of full scale, not at full scale. That. The transition to the maximum value at the output does not occur at full scale voltage, but at a value less than the least significant digit (LSB) than the input full scale voltage. The transfer characteristic can be implemented with a -1/2 LSB offset. This is achieved by shifting the transfer characteristic to the left, which shifts the quantization error from -1...0 LSB to -1/2...+1/2 LSB.

Rice. 8. Transfer characteristic of a 3-bit ADC offset by -1/2LSB

Due to the technological spread of parameters in the manufacture of integrated circuits, real ADCs do not have an ideal transfer characteristic. Deviations from the ideal transfer characteristic determine the static error of the ADC and are given in the technical documentation.

The ideal transfer characteristic of the ADC crosses the origin, and the first code transition occurs when the value of 1 LSB is reached. Additive error (offset error) can be defined as the shift of the entire transfer characteristic to the left or right relative to the input voltage axis, as shown in Fig. 9. Thus, a 1/2 LSB offset is deliberately included in the definition of additive ADC error.

Rice. 9. Additive error (Offset Error)

Multiplicative error

The multiplicative error (full scale error) is the difference between the ideal and actual transfer characteristics at the point of maximum output value under the condition of zero additive error (no offset). This manifests itself as a change in the slope of the transfer function, which is illustrated in Fig. ten.

Rice. 10. Multiplicative error (Full-Scale Error)

For an ideal ADC transfer characteristic, the width of each "step" should be the same. The difference in the length of the horizontal segments of this piecewise linear function of 2N "steps" is a differential non-linearity (DNL).

The value of the least significant bit of the ADC is Vref/2N, where Vref is the reference voltage, N is the resolution of the ADC. The voltage difference between each code transition must be equal to the value of LSB. The deviation of this difference from LSB is defined as differential non-linearity. In the figure, this is shown as unequal gaps between "steps" of the code, or as "blurring" of transition boundaries on the ADC transfer characteristic.

Rice. 11. Differential non-linearity (DNL)

Integral non-linearity

Integral non-linearity (INL) is an error that is caused by the deviation of the linear function of the ADC transfer characteristic from a straight line, as shown in Fig. 12. Typically, a transfer function with an integral non-linearity is approximated by a straight line using the least squares method. Often the fitting straight line simply connects the smallest and largest values. The integral nonlinearity is determined by comparing the voltages at which code transitions occur. For an ideal ADC, these transitions will occur at input voltages that are exactly multiples of LSB. And for a real converter, such a condition can be met with an error. The difference between the "ideal" voltage levels at which the code transition occurs and their real values ​​is expressed in LSB units and is called the integral nonlinearity.

Rice. 12. Integral non-linearity (INL)

Quantization error

One of the most significant error components in ADC measurements, quantization error, is the result of the conversion process itself. Quantization error is the error caused by the value of the quantization step and is defined as? least significant digit (LSB) value. It cannot be excluded in analog-to-digital conversions, since it is an integral part of the conversion process, it is determined by the resolution of the ADC and does not change from ADC to ADC with equal resolution.

Dynamic characteristics

The dynamic characteristics of an ADC are usually determined using spectral analysis, from the results of performing a fast Fourier transform (FFT) on an array of ADC output values ​​corresponding to some test input signal.

On fig. 13 shows an example of the frequency spectrum of the measured signal. The zero harmonic corresponds to the fundamental frequency of the input signal. Everything else is noise, which includes harmonic distortion, thermal noise, 1/f noise, and quantization noise. Some noise components are generated by the ADC itself, some may be input to the ADC from external circuits. Harmonic distortion, for example, can be contained in the measured signal and simultaneously generated by the ADC during the conversion process.

Rice. 13. The result of the FFT execution on the output data of the ADC

Signal-to-noise ratio

The signal-to-noise ratio (SNR) is the ratio of the RMS value of the input signal to the RMS value of the noise (excluding harmonic distortion), expressed in decibels:

SNR(dB) = 20 log [ Vsignal(rms)/ Vnoise(rms) ]

This value allows you to determine the proportion of noise in the measured signal in relation to the useful signal.

Rice. 14. SNR - Signal to Noise Ratio

Rice. 15. FFT Reflects Harmonic Distortion

The noise measured in the SNR calculation does not include harmonic distortion, but does include quantization noise. For an ADC with a certain resolution, it is quantization noise that limits the capabilities of the converter to a theoretically better signal-to-noise ratio, which is defined as:

SNR(db) = 6.02 N + 1.76,

where N is the resolution of the ADC.

The ADC quantization noise spectrum of standard architectures has a uniform frequency distribution. Therefore, the magnitude of this noise cannot be reduced by increasing the conversion time and then averaging the results. Quantization noise can only be reduced by making measurements with a larger ADC.

A feature of the sigma-delta ADC is that its quantization noise spectrum is unevenly distributed over frequency - it is shifted towards high frequencies. Therefore, by increasing the measurement time (and, accordingly, the number of samples of the measured signal), accumulating and then averaging the obtained sample (low-pass filter), one can obtain a measurement result with a higher accuracy. Naturally, in this case, the total conversion time will increase.

Other sources of ADC noise include thermal noise, 1/f noise, and reference jitter.

General harmonic distortion

Non-linearity in the results of data conversion leads to the appearance of harmonic distortion. Such distortions are observed as "emissions" in the frequency spectrum at even and odd harmonics of the measured signal (Fig. 15).

This distortion is defined as total harmonic distortion (THD). They are defined as:

The amount of harmonic distortion decreases at high frequencies to the point where the amplitude of the harmonics becomes less than the noise level. Thus, if we analyze the contribution of harmonic distortion to the conversion results, this can be done either in the entire frequency spectrum, while limiting the amplitude of the harmonics by the noise level, or by limiting the bandwidth for analysis. For example, if our system has a low-pass filter, then we are simply not interested in high frequencies and high-frequency harmonics are not subject to accounting.

Signal-to-noise ratio and distortion

Signal-to-noise and distortion ratio (SiNAD) more fully describes the noise characteristics of an ADC. SiNAD takes into account the amount of both noise and harmonic distortion in relation to the useful signal. SiNAD is calculated using the following formula:

Rice. 16. Dynamic range free from harmonics

The ADC specification, given in the technical documentation for microcircuits, helps to reasonably select a converter for a particular application. As an example, consider the specification of the ADC integrated into the new C8051F064 microcontroller manufactured by Silicon Laboratories.

Microcontroller C8051F064

The C8051F064 crystal is a high-speed 8-bit microcontroller for joint processing of analog and digital signals with two integrated 16-bit successive approximation ADCs. Built-in ADCs can operate in single-wire and differential modes with a maximum performance of up to 1M samples/sec. The table shows the main characteristics of the ADC of the C8051F064 microcontroller. To evaluate the C8051F064's digital and analog processing capabilities on your own, you can use the inexpensive C8051F064EK evaluation kit (Figure 17). The kit includes an evaluation board based on the C8051F064, a USB cable, documentation, and software for testing the analog dynamic and static characteristics of an integrated high-precision 16-bit ADC.

Table. V DD = 3.0 V, AV+ = 3.0 V, AVDD = 3.0 V, V REF = 2.50 V (REFBE=0), -40 to +85° unless otherwise noted

Rice. 17. Evaluation kit C8051F064EK

Literature

1. http://www.wbc-europe.com/en/services/pim_application_guide.html
2. www.silabs.com

Wolfgang Reis (WBC GmbH)

Lecture #3

"Analog-to-digital and digital-to-analog conversion".

In microprocessor systems, the role of a pulse element is performed by an analog-to-digital converter (ADC), and the role of an extrapolator is performed by a digital-to-analog converter (DAC).

Analog to digital conversion is to convert the information contained in the analog signal into a digital code . Digital to analog conversion designed to perform the inverse task, i.e. convert a number represented as a digital code into an equivalent analog signal.

ADCs, as a rule, are installed in the feedback circuits of digital control systems to convert analog feedback signals into codes that are perceived by the digital part of the system. That. ADCs perform several functions, such as: temporal sampling, level quantization, encoding. A generalized block diagram of the ADC is shown in Fig. 3.1.

A signal in the form of current or voltage is applied to the input of the ADC, which is quantized by level during the conversion process. The ideal static response of a 3-bit ADC is shown in Figure 3.2.

The input signals can take on any value in the range from − Umax to Umax , and the outputs correspond to eight (2 3) discrete levels. The value of the input voltage at which there is a transition from one value of the ADC output code to another adjacent value is called code transition voltage. The difference between two adjacent values ​​of intercode transitions is called quantization step or unit of least significant digit (LSD).Starting point of the conversion characteristic is called a point defined by the value of the input signal, defined as

(3.1),

where U 0.1 is the voltage of the first intercode transition, ULSB – quantization step ( LSB - Least Significant Bit ). conversion corresponds to the input voltage, determined by the ratio

(3.2).

ADC input voltage range, limited by values U 0.1 and U N-1,N called input voltage range.

(3.3).

Input voltage range and LSB value N -bit ADC and DAC links ratio

(3.4).

Voltage

(3.5)

called full scale voltage ( FSR-Full Scale Range ). Typically, this parameter is determined by the output signal level of the voltage reference connected to the ADC. The value of the quantization step or the unit of the least significant bit, i.e. is equal to

(3.6),

and the unit value of the most significant digit

(3.7).

As can be seen from Fig. 3.2, during the conversion, an error occurs that does not exceed half the value of the least significant digit U LSB /2.

There are various methods of analog-to-digital conversion, which differ in accuracy and speed. In most cases, these characteristics are antagonistic to each other. At present, such types of converters as ADCs of successive approximations (bitwise balancing), integrating ADCs, parallel ( Flash ) ADC, "sigma-delta" ADC, etc.

The block diagram of the ADC of successive approximations is shown in Fig.3.3.

The main elements of the device are a comparator (K), a digital-to-analog converter (DAC) and a logic control circuit. The conversion principle is based on sequential comparison of the input signal level with the signal levels corresponding to various combinations of the output code and the formation of the resulting code based on the results of the comparisons. The sequence of compared codes satisfies the rule of half division. At the beginning of the conversion, the input code of the DAC is set to a state in which all bits except the highest bit are 0, and the highest bit is 1. With this combination, a voltage equal to half the input voltage range is generated at the DAC output. This voltage is compared with the input voltage at the comparator. If the input signal is greater than the signal coming from the DAC, then the most significant bit of the output code is set to 1, otherwise it is reset to 0. At the next cycle, the code partially formed in this way is again fed to the DAC input, the next bit is set to one and comparison repeats. The process continues until the least significant bit is compared. That. to form N - bit output code needed N identical elementary cycles of comparison. This means that, other things being equal, the speed of such an ADC decreases with an increase in its capacity. The internal elements of the successive approximation ADC (DAC and comparator) must have accuracy better than half the LSB of the ADC.

Structural diagram of a parallel ( Flash ) ADC is shown in Figure 3.4.

In this case, the input voltage is applied for comparison to the inputs of the same name immediately. N -1 comparators. The opposite inputs of the comparators receive signals from a high-precision voltage divider, which is connected to a reference voltage source. In this case, the voltages from the outputs of the divider are evenly distributed along the entire range of the input signal. The priority encoder generates a digital output corresponding to the highest comparator with the output enabled. That. to provide N -bit conversion needed 2 N divider resistors and 2 N -1 comparator. This is one of the fastest conversion methods. However, with a large capacity, it requires large hardware costs. The accuracy of all divider resistors and comparators should again be better than half the value of the least significant bit.

The block diagram of the double integration ADC is shown in Figure 3.5.

The main elements of the system are an analog switch, consisting of keys SW 1, SW 2, SW 3, integrator I, comparator K and counter C. The conversion process consists of three phases (Fig. 3.6).

The key is closed in the first phase SW 1, and the rest of the switches are open. Through a private key SW 1, an input voltage is applied to an integrator that integrates the input signal over a fixed time interval. After this time interval, the level of the output signal of the integrator is proportional to the value of the input signal. At the second stage of the transformation, the key SW 1 opens, and the key SW 2 is closed, and a signal from the reference voltage source is applied to the input of the integrator. The integrator capacitor discharges from the voltage accumulated in the first conversion interval at a constant rate proportional to the reference voltage. This stage lasts until the integrator output voltage drops to zero, as evidenced by the output signal of the comparator comparing the integrator signal with zero. The duration of the second stage is proportional to the input voltage of the converter. During the entire second stage, high-frequency pulses with a calibrated frequency are fed to the counter. That. after the second stage, the digital readings of the counter are proportional to the input voltage. With this method, very good accuracy can be achieved without placing high demands on the accuracy and stability of the components. In particular, the stability of the integrator capacitance may not be high, since the charge and discharge cycles occur at a rate inversely proportional to the capacitance. Furthermore, comparptor drift and offset errors are compensated by having each conversion step start and end at the same voltage. To improve the accuracy, the third stage of the transformation is used, when the input of the integrator through the key SW 3 is a zero signal. Since the same integrator and comparator are used at this stage, subtracting the output error value at zero from the result of the subsequent measurement allows one to compensate for errors associated with measurements near zero. Strict requirements are not imposed even on the frequency of clock pulses supplied to the counter, because a fixed time interval at the first stage of the conversion is formed from the same pulses. Strict requirements are imposed only on the discharge current, i.e. to the reference voltage source. The disadvantage of this method of conversion is the low speed.

ADCs are characterized by a number of parameters that make it possible to implement the choice of a specific device based on the requirements for the system. All ADC parameters can be divided into two groups: static and dynamic. The former determine the accuracy characteristics of the device when working with a constant or slowly changing input signal, and the latter characterize the speed of the device as maintaining accuracy with increasing frequency of the input signal.

The quantization level lying in the vicinity of zero of the input signal corresponds to the voltages of intercode transitions –0.5 U LSB and 0.5 U LSB (the first occurs only in the case of a bipolar input signal). However, in real devices, the voltages of these intercode transitions may differ from these ideal values. The deviation of the real levels of these voltages of intercode transitions from their ideal values ​​is called bipolar zero offset error ( Bipolar Zero Error ) and unipolar zero offset error ( Zero Offset Error ) respectively. With bipolar ranges, conversions usually use a zero offset error, and with unipolar ones, a unipolar offset error. This error leads to a parallel shift of the real transformation characteristic relative to the ideal characteristic along the abscissa axis (Fig. 3.7).

Deviation of the input signal level corresponding to the last intercode transition from its ideal value U FSR -1.5 U LSB , is called full scale error ( Full Scale Error ).

ADC conversion factor is called the tangent of the slope of the straight line drawn through the start and end points of the real transformation characteristic. The difference between the actual and ideal value of the conversion factor is called conversion factor error ( Gain Error ) (Fig. 3.7). It includes errors at the ends of the scale, but does not include zero errors of the scale. For a unipolar range it is defined as the difference between the full scale error and the unipolar zero offset error, and for a bipolar range it is the difference between the full scale error and the bipolar zero offset error. In fact, in any case, this is the deviation of the ideal distance between the last and first intercode transitions (equal to U FSR -2 U LSB ) from its real value.

Zero offset and conversion factor errors can be compensated for by adjusting the ADC preamplifier. To do this, you must have a voltmeter with an accuracy of at least 0.1 ULSB . For the independence of these two errors, the zero offset error is corrected first, and then the transform coefficient error.To correct the ADC zero offset error, you must:

1. Set the input voltage to exactly 0.5 U LSB ;

2. Adjust the ADC preamplifier offset until the ADC switches to state 00…01.

To correct the conversion coefficient error, you must:

1. Set the input voltage exactly at the level U FSR -1.5 U LSB ;

2. Adjust the ADC preamplifier gain until the ADC switches to state 11…1.

Due to the imperfection of the elements of the ADC circuit, the steps at different points of the ADC characteristics differ from each other in magnitude and are not equal U LSB (Fig. 3.8).

Deviation of the distance between the midpoints of two adjacent real quantization steps from the ideal value of the quantization step ULSB called differential nonlinearity (DNL - Differential Nonlinearity). If DNL greater than or equal ULSB , then the ADC may have so-called “missing codes” (Fig. 3.3). This entails a local sharp change in the ADC transmission coefficient, which in closed control systems can lead to loss of stability.

For those applications where it is important to maintain the output signal with a given accuracy, it is important that the ADC output codes match the voltages of intercode transitions as closely as possible. The maximum deviation of the quantization step center on the real ADC characteristic from the linearized characteristic is called integral nonlinearity (INL - Integral Nonlinearity) orrelative accuracy (Relative Accuracy) ADC (Figure 3.9).

The linearized characteristic is drawn through the extreme points of the real transformation characteristic, after they have been calibrated, i.e. eliminated zero offset and conversion factor errors.

It is practically impossible to compensate for errors in differential and integral nonlinearity by simple means.

ADC resolution ( Resolution ) is the reciprocal of the maximum number of code combinations at the ADC output

(3.8).

This parameter determines what minimum input signal level (relative to the full amplitude signal) the ADC is able to accept.

Accuracy and resolution are two independent characteristics. Resolution plays a decisive role when it is important to provide a given dynamic range of the input signal. Accuracy is decisive when it is required to maintain the controlled value at a given level with a fixed accuracy.

ADC dynamic range (DR - Dynamic Range ) is the ratio of the maximum perceived input voltage level to the minimum, expressed in dB

(3.9).

This parameter determines the maximum amount of information that the ADC is capable of transmitting. So, for a 12-bit ADC DR=72 dB.

The characteristics of real ADCs differ from the characteristics of ideal devices due to the imperfection of the elements of a real device. Let's consider some parameters that characterize real ADCs.

signal-to-noise ratio(SNR - Signal to Noise Ratio ) is the ratio of the RMS value of the input sinusoidal signal to the RMS value of the noise, which is defined as the sum of all other spectral components up to half the sampling frequency, excluding the DC component. For the perfect N -bit ADC that generates only quantization noise SNR , expressed in decibels, can be defined as

(3.10),

where N - bit depth of the ADC. So, for a 12-bit ideal ADC SNR =74 dB. This value is greater than the dynamic range value of the same ADC. the minimum level of the perceived signal must be greater than the noise level. This formula takes into account only quantization noise and does not take into account other sources of noise that exist in real ADCs. Therefore, the values SNR for real ADCs, as a rule, it is less than ideal. typical value SNR for a real 12-bit ADC is 68-70 dB.

If the input signal has a swing less U FSR , then the last formula needs to be corrected

(3.11),

where KOS is the attenuation of the input signal, expressed in dB. So, if the input signal of a 12-bit ADC has an amplitude 10 times less than half the full scale voltage, then KOS = -20 dB and SNR=74dB - 20dB=54dB.

Real value SNR can be used for determining the effective number of ADC bits( ENOB - Effective Number of Bits ). It is determined by the formula

(3.12).

This indicator can characterize the actual decision power of a real ADC. So, a 12-bit ADC, which has SNR =68dB for a signal with FOS=-20dB is actually 7-bit ( ENOB=7.68). ENOB value strongly depends on the frequency of the input signal, i.e. the effective bit depth of the ADC decreases with increasing frequency.

Total harmonic distortion ( THD – Total Harmonic Distortion ) is the ratio of the sum of the RMS values ​​of all higher harmonics to the RMS value of the fundamental harmonic

(3.13),

where n usually limit at level 6 or 9. This parameter characterizes the level of harmonic distortion of the output signal of the ADC compared to the input. THD increases with the frequency of the input signal.

Full power bandwidth ( FPBW - Full Power Bandwidth ) is the maximum peak-to-peak input frequency at which the amplitude of the reconstructed fundamental is reduced by no more than 3 dB. As the frequency of the input signal increases, the analog ADC circuits no longer have time to work out its changes with a given accuracy, which leads to a decrease in the ADC conversion coefficient at high frequencies.

Settling time (Setting time ) is the time required for the ADC to reach its nominal accuracy after a step signal with an amplitude equal to the full range of the input signal has been applied to its input. This parameter is limited due to the finite speed of various ADC nodes.

Due to various kinds of errors, the characteristic of a real ADC is non-linear. If a signal is applied to the input of a device with nonlinearities, the spectrum of which consists of two harmonics f a and f b , then in the spectrum of the output signal of such a device, in addition to the fundamental harmonics, there will be intermodulation subharmonics with frequencies, where m , n =1,2,3,… Second-order subharmonics are f a + f b , f a - f b , subharmonics of the third order are 2 f a + f b , 2 f a - f b , f a +2 f b , f a -2 f b . If the input sinusoids have close frequencies located near the upper edge of the bandwidth, then the second order subharmonics are far away from the input sinusoids and are located in the lower frequency region, while the third order subharmonics have frequencies close to the input frequencies.

Intermodulation distortion factor ( Intermodular Distortion ) is the ratio of the sum of the RMS values ​​of intermodulation subharmonics of a certain order to the sum of the RMS values ​​of the fundamental harmonics, expressed in dB

(3.14).

Any method of analog-to-digital conversion requires some finite time to complete. Under ADC conversion time ( Conversion Time ) refers to the time interval from the moment the analog signal arrives at the ADC input until the corresponding output code appears. If the input signal of the ADC changes in time, then the final conversion time of the ADC leads to the appearance of the so-called. aperture error(fig.3.10).

The conversion start signal arrives at the moment t0 , and the output code appears at the moment t1 . During this time, the input signal managed to change by the valueD U . Uncertainty arises: what level of the value of the input signal in the range U 0 - U 0 + D U corresponds to the given output code. To maintain the conversion accuracy at the level of the least significant digit, it is necessary that during the conversion the change in the signal value at the ADC input would be no more than the value of the least significant digit

(3.15).

The change in signal level over the conversion time can be roughly calculated as

(3.16),

where U in – ADC input voltage, Tc - conversion time. Substituting (3.16) into (3.15) we get

(3.17).

If the input is a sinusoidal signal with a frequency f

(3.18),

then its derivative will be

(3.19).

It takes on a maximum value when the cosine is equal to 1. Substituting (3.9) into (3.7) taking this into account, we obtain

, or

(3.20)

The finite conversion time of the ADC leads to the requirement to limit the rate of change of the input signal. In order to reduce the aperture error, etc. weaken the limit on the rate of change of the ADC input signal at the input of the converter is set to the so-called. "sample-hold device" (SHA) ( Track/Hold Unit ). A simplified diagram of the UVH is shown in Fig. 3.11.

This device has two modes of operation: sampling mode and latching mode. The sampling mode corresponds to the closed state of the key SW . In this mode, the SHA output voltage repeats its input voltage. The locking mode is activated by a command that opens the key SW . In this case, the connection between the input and output of the SHA is interrupted, and the output signal is maintained at a constant level corresponding to the level of the input signal at the moment the lock command is received due to the charge accumulated on the capacitor. Thus, if a freeze command is issued just before the start of the ADC conversion, the SHA output signal will be maintained at a constant level during the entire conversion time. After the conversion is completed, the SHA is switched back to the sampling mode. The operation of a real SHA is somewhat different from the ideal case, which was described (Fig. 3.12).

(3.21),

where f is the frequency of the input signal, t A is the magnitude of the aperture uncertainty.

In real SHA, the output signal cannot remain absolutely unchanged during a finite conversion time. The capacitor will be gradually discharged by the small input current of the output buffer. To maintain the required accuracy, it is necessary that during the conversion the charge of the capacitor does not change by more than 0.5 ULSB.

Digital-to-analog converters are usually installed at the output of a microprocessor system to convert its output codes into an analog signal supplied to a continuous control object. The ideal static response of a 3-bit DAC is shown in Figure 3.13.

Characteristic starting point defined as the point corresponding to the first (zero) input code U 00…0 . Characteristic end point defined as the point corresponding to the last input code U 11…1 . The definitions of the output voltage range, LSB unit, zero offset error, conversion ratio error are similar to those of the ADC.

From the point of view of the structural organization, the DAC has a much smaller variety of options for building a converter. The main structure of the DAC is the so-called. “chain R -2 R scheme” (Fig. 3.14).

It is easy to show that the input current of the circuit is I in = U REF / R , and the currents of the successive links of the circuit, respectively I in /2, I in /4, I in /8 etc. To convert the input digital code into an output current, it is enough to collect all the currents of the arms corresponding to units in the input code at the output point of the converter (Fig. 3.15).

If an operational amplifier is connected to the output point of the converter, then the output voltage can be determined as

(3.22),

where K – input digital code, N - bit depth of the DAC.

All existing DACs are divided into two large groups: DAC with current output and DAC with voltage output. The difference between them lies in the absence or presence of the final stage on the operational amplifier in the DAC chip. Voltage output DACs are more complete devices and require fewer additional components to operate. However, the final stage, along with the parameters of the ladder circuit, determines the dynamic and accuracy parameters of the DAC. It is often difficult to implement an accurate high-speed operational amplifier on the same chip with a DAC. Therefore, most high-speed DACs have a current output.

Differential non-linearity for DAC is defined as the deviation of the distance between two adjacent levels of the analog output signal from the ideal value ULSB . A large value of differential non-linearity can cause the DAC to become non-monotonic. This means that an increase in the digital code will lead to a decrease in the output signal in some part of the characteristic (Fig. 3.16). This can lead to unwanted generation in the system.

Integral non-linearity for a DAC, it is defined as the largest deviation of the analog output signal level from a straight line drawn through the points corresponding to the first and last code, after they are adjusted.

Settling time DAC is defined as the time for which the output signal of the DAC will be set at a given level with an error of no more than 0.5 ULSB after the input code has changed from the value 00…0 to the value 11…1. If the DAC has input registers, then a certain part of the settling time is due to a fixed delay in the passage of digital signals, and only the remaining part is due to the inertia of the DAC circuit itself. Therefore, the settling time is usually measured not from the moment a new code arrives at the DAC input, but from the moment the output signal corresponding to the new code begins to change, until the moment the output signal is established with an accuracy of 0.5U LSB (fig.3.17) .

In this case, the settling time determines the maximum sampling frequency of the DAC.

(3.23),

where t S - settling time.

Digital DAC input circuits have a finite speed. In addition, the speed of propagation of signals corresponding to different bits of the input code is not the same due to the spread of the parameters of the elements and circuit features. As a result, the arms of the ladder circuit of the DAC, when a new code arrives, do not switch synchronously, but with some delay relative to each other. This leads to the fact that in the DAC output voltage diagram, when moving from one steady value to another, spikes of various amplitudes and directions are observed (Fig. 3.18).

According to the operation algorithm, the DAC is a zero-order extrapolator, the frequency response of which can be represented by the expression

(3.24),

where w s - sampling frequency. The frequency response of the DAC is shown in Figure 3.20.

As can be seen, at a frequency of 0.5w s the recovered signal is attenuated by 3.92 dB compared to the low frequency components of the signal. Thus, there is a slight distortion of the spectrum of the restored signal. In most cases, this small distortion does not significantly affect the system parameters. However, in cases where increased linearity of the spectral characteristics of the system is required (for example, in sound processing systems), to equalize the resulting spectrum at the output of the DAC, it is necessary to install a special recovery filter with a frequency response of the type x/sin(x).